The present invention relates to an apparatus such as a cable modem and a method which support two-way communication of data packets between a head-end system and the cable modem in a Time Division Multiplexed System. A communication channel such as a Hybrid Fibre Coaxial (HFC) channel or a microwave link may be utilised by a service provider to transmit information to homes of multiple users and simultaneously provide a narrow band return channel for each user""s data to the service provider.
In particular, the present invention relates to an interface unit and method which are capable of supporting a software implemented management of received/transmitted data packets within a cable modem operating in the Time Division Multiplexed System.
With the recent rise in popularity of the Internet and other public or dedicated networks for electronic information exchange, many home computer users are using a modem to access e.g. the Internet through a Public Switched Telephone Network (PSTN) using home telephone lines. In this situation, the PSTN provides a dedicated communication path or circuit from the user""s modem to a server located at e.g. an Internet Service Provider. The server functions as a gateway to the Internet. However, the bandwidth of typical home telephone lines is relatively small and/or the modems are typically capable of operating only at channel bit rates below approximately 56 Kbit/s, which limits the speed at which information can be received. Other modem technologies based on the PSTN such as ADSL require that the service provider installs a dedicated modem for each connected user, due to the need for a dedicated communication channel to each user""s home. As an alternative to using telephone lines, the Internet can be accessed through HFC channels using a cable modem or a set-top box. HFC channels may provide much greater bandwidth than home telephone lines and are widely available to existing cable television subscribers. However, unlike telephone lines, existing HFC channel infrastructure does typically not provide a dedicated path or channel to the home of the users. Instead, multiple users are usually coupled to the same HFC channel leading to a head-end system which may be located at an Internet Service Provider""s site. In addition, analogue or digital television signals are also frequently sent on the same HFC channel. Therefore, Internet service providers that use HFC channels must send and receive both data packets that contain information data, and control packets. The control packets provide the cable modem with information needed to send and receive the data packets, such as what carrier frequency outgoing or upstream packets from the cable modem should be transmitted on, what should its transmitter power level be, how many packets may be transmitted, what data packets on the HFC channel are intended for the cable modem, etc. Accordingly, the control packets provide a mechanism that allows a plurality of users organised in a shared-channel type of structure to communicate with the head-end system. The shared structure typically allows as many as one thousand users to simultaneously communicate with a single common modem forming part of the head-end system. Furthermore, the use of the shared channel provides statistical relief for burst traffic typically generated by Internet applications, so to an Internet user, it may appear that the entire downstream and upstream bandwidths are available on request. Accordingly, by utilising cable modem technology, a service provider can deliver cost effective high speed data communication services to thousands of users with a relatively limited investment in modem hardware and by utilising the existing HFC channel infrastructure.
An important class of cable modems are those operating according to the specifications provided by the European Telecommunications Standards Institute (ETSI) in ETS 300 800: Digital Video Broadcast Interaction Channel for Cable TV Distribution Systems. This specification details a Time Division Multiplexed System for two-way data communication between a head-end system in this context denoted an Interactive Network adapter (INA) and multiple cable modems denoted Network Interface Units (NIUs) located at the homes of the users. The upstream transfer of data from the plurality of users allocated to a particular INA may be divided into time slots and each time slot allocated to a particular user of the multiple users, by utilising Time Division Multiple Access (TDMA) techniques. The TDMA protocol specified in the DVB standard utilises a slotting methodology which allows transmit start times of each of the multiple of NIUs to be synchronised to a common clock source provided by the INA. Synchronising the start times increases message throughput of the shared data channel since the transmitted data packets do not overlap during transmission.
According to the DVB standard, control packets are denoted Media Access Control (MAC) packets or frames. Each NIU contains a unique MAC address which may be hard-coded into the NIU. Consequently, dedicated data may be transmitted from the INA to any particular users cable modem or NIU operating in the data transmission network. Synchronisation of upstream data packets is provided by transmitting some MAC frames which contain a specific time indicator for upstream synchronisation of slots. This time indicator contains information that allows a modem CPU or other data processor to calculate the time at which the modem is allowed to transmit an outgoing data frame to the head-end system if the arrival time of the MAC frame containing the indicator is known. A MAC frame containing the time indicator shall be sent at least in every time period of 3 ms according to the DVB standard. Accordingly, the time indicators provide a mechanism that allows NIUs to operate with the same time reference or clock so that the INA can assign time slots to different users"" modems so as to avoid collision of data between different users. However, since there is a slightly different propagation delay between the NIUs in the data transmission network, a time base ranging method must be utilised to compensate for this NIU specific delay. Each NIU is provided by a specific delay time value which has been measured by the INA in a communication session comprising transmitting upstream ranging frames.
Prior art cable modems or set-top boxes have traditionally been based on specialised processors and various dedicated circuitry for receiving and processing incoming data packets as well as generating, encoding etc. outgoing data packets. These specialised processors have traditionally been hard-wired so as to apply a dedicated decoding process, i.e. a substantially fixed set of operations, to the received data packets in correspondence with the communication protocol of the network in question. The hardwired processors have typically been manufactured in CMOS technology as standard-cell designs or gate-array designs since these design methods are capable of providing the number of gates and/or gate density required for such complex Application Specific Integrated Circuits (ASICs). The hard-wiring has previously been assumed necessary to accommodate real time requirements for downstream data packet reception and decoding and for upstream data packet generation and encoding imposed by the high data rate of the received/transmitted data packets. In MPEG transport streams, the data rate of received or down stream data packets at the NIU or cable modem is typically about 42-56 Mbit/s while the upstream/transmitted data rate from the NIU to the INA is about 256 Kbit/s-3.088 Mbit/s.
There are several drawbacks related to the use of hardwired processors in cable modems. One drawback is that a substantial time period is required to designing, manufacturing, testing and production preparing a new or upgraded hard-wired processor. Such upgraded processors are often required to implement a new/revised or enhanced communication protocol or just to keep up with evolving communication protocols. For a new communication product, such as a cable modem, a long time-to-market is of course damaging for the profits that a manufacturer can expect from the product sales during its life cycle. Another drawback of the hard-wired approach is that debugging of new designs during e.g. prototype testing is quite difficult. This is due to the hard-wired architecture of the processor that makes it difficult, and thereby time consuming, or even impossible to modify processing steps in the processor and monitor whether any observed error in the data processing.
In contrast, a cable modem according to the present invention may provide a highly flexible protocol handling of two-way data communication between e.g. a cable modem and a head-end system. This flexibility may be accomplished by utilising a software controlled microprocessor to manage the decoding and processing of received data packets as well as to generate and encode outgoing data packets. A such software controlled management of data packets further provides a significant decrease in development time and development costs of new generations of cable modems offering new and/or enhanced features.
It is an object of the invention to provide an apparatus and a method which facilitate a flexible management of data packets in a Time Division Multiplexed System for data communication.
It is also an object of the invention to provide an apparatus, which can rapidly be adapted to evolving communication protocols, and as such provide short time-to-markets for new and/or enhanced apparatuses. Consequently, the present invention is capable of rapidly providing compatible e.g. cable modems to the market in response to revisions of existing communication protocols and to development of new communication protocols.
A basic philosophy of the apparatus and the method provided by the present invention has been to provide a solution wherein the management, such as reception, decoding, generation and encoding of data packets, may be controlled by software running on e.g. a microprocessor rather than being controlled by a dedicated hard-wired processor operating according to a number of fixed and predetermined processing steps.
One aspect of the invention relates to an apparatus for two-way communication of data in a time division multiplexed system, and comprising
clock generator means for generating first and second clock signals,
processor means for receiving the first clock signal and processing received data packets,
an interface unit for receiving and intermediately storing incoming data packets from a head-end system and for intermediately storing and transmitting outgoing data packets to the head-end system, the interface unit comprising:
time base means for receiving the second clock signal and generating a current time stamp value,
input buffer means for receiving data of the incoming data packets, the input buffer means comprising:
means for sampling the current time stamp value and associating the value with at least some of the incoming data packets, the time stamp value indicating an arrival time of the respective data packet, and
data transfer means adapted to transmit data of the incoming data packets with any associated time stamps to a memory of the interface unit, and
output buffer means for transmitting data of the outgoing data packets and comprising:
data transfer means adapted to receive data of the outgoing data packets with associated time stamps from the memory of the interface unit, and
means for comparing the time stamp value of each outgoing data packet with the current time stamp value, and for transmitting an outgoing data packet to the head-end system when said values match a predetermined relationship,
the processor means being adapted to generate and associate the output time stamp with each outgoing data packet, the output time stamp indicating a departure time of the data packet, the output time stamp value being related to input time stamp values of selected incoming data packets.
thereby permitting correct time-slot alignment of outgoing data packets in the time division multiplexed system.
In the present specification and claims, the term xe2x80x9capparatusxe2x80x9d designates one or several pieces of electronic equipment which, as a whole, comprise(s) all the units, modules or circuit blocks that characterise the invention as stated above. Accordingly, the apparatus may appear as a distributed system where individual modules or units are not located in close physical proximity to each other. As an example of this architecture, the interface unit may be physically located on e.g. a Personal Computer (PC) card of a first PC while the processor means may be located on another circuit board or card of the same PC, or even within a second PC sharing a communication channel with the first PC. Furthermore, the processor means may, in this context, be constituted by an existing microprocessor of the first and/or second PC which transfers the incoming/outgoing data packets to/from the interface unit over an existing data bus within the PC, e.g. an industry standard PCI bus as commonly provided in today""s PCs. In this situation, the microprocessor may run a data packet management program responsible for managing the received/transmitted data packets of the time division multiplexed communication system at the same time as running ordinary application programs such as word processing programs, Internet browser programs, spreadsheet programs etc.
The term xe2x80x9capparatusxe2x80x9d also designates a substantially self-contained piece of electronic equipment such as a cable modem or set-top box substantially comprising all the relevant modules or circuit blocks in close physical proximity of each other within a dedicated housing or casing. In this situation, a software controlled industry standard microprocessor such as a PowerPC(copyright) or a Pentium(copyright) processor or any other suitable RISC/embedded processor may be provided to manage generation, decoding etc. of the received/transmitted data packets.
The interface unit may comprise a dedicated memory area or device that intermediately stores the incoming data packets including packets with associated time stamps. Alternatively, the incoming data packets may be stored in a memory area which is allocated in an existing memory structure or area in the apparatus, such as a system memory area utilised by the processor means for e.g. application program storage and/or data storage. In the last situation, the interface unit additionally comprises that allocated area of the system memory and the term xe2x80x9cinterface unitxe2x80x9d mostly refers to a logical partitioning of the present apparatus rather than referring to any particular hardware partitioning of the system. The input buffer means that stores data of the incoming data packets and generates associated time stamps may be adapted to solely store a few bytes, such as 4-128 bytes or more preferably 16-64 bytes, of an incoming data packet at time. The transfer of the complete incoming data packet as well as any associated time stamp may be accomplished by transferring a number of xe2x80x9cdata portionsxe2x80x9d to the memory provided therefore in the interface unit. Alternatively, the input buffer means may store one or several complete and, optionally, time stamped data packets before it/they is/are transferred to the interface unit memory. The input buffer means and the output buffer means may have a number of associated device registers which may control specific parameters of the data reception and transmission processes, e.g. starting or suspending the reception of incoming data packets, the number of bytes of an incoming data packets which is stored at a time in the input and or output buffer means and activating a frame header filter etc. The device registers are preferably available for reading and writing by a data packet management program running on the processor means so that the parameters of the data reception and transmission processes can be modified in software.
In the present specification and claims, the term xe2x80x9cprocessor meansxe2x80x9d designates any conventional or proprietary processor or microprocessor such as a hardwired proprietary processor or finite state machine, Read Only Memory (ROM) or software programmable microprocessor as well as combinations thereof capable of providing the required management of received/transmitted data packets. According to a preferred embodiment of an apparatus according to the invention, the processor means are provided in the form of an embedded PowerPC(copyright) microprocessor comprised within an ASIC that integrates most of a functionality of a cable modem adapted for operation in a Time Division Multiplexed System operating according to the communication standard set forth in ETS 300 800.
Each outgoing data packet is provided with an associated output time stamp value indicating a departure time of the data packet. This association may be implemented by a number different methodologies. The processor may directly generate and insert the relevant output time stamp value into each outgoing data packet at a predetermined position in the packet and subsequently transfer the time stamped outgoing packet to the interface unit memory area. The output buffer means may be adapted to read and transfer the outgoing packets to the output buffer means. The time stamp insertion in the outgoing data packets may be performed before or after the data or xe2x80x9ccontentxe2x80x9d of the packet has been generated or determined by the processor, since the value of the time stamp is determined based on arrival time information of selected incoming data packets. The output time stamp value associated with each outgoing data packet may also be generated by the processor means in a coded format so that a xe2x80x9ccoding data packetxe2x80x9d may contain information relating to the departure time of one or several subsequent packets or even preceding packets (which may still be stored in the output buffer means awaiting departure). In this situation, the one or several subsequent or preceding packets may not need a time stamp of their own, since these packets are provided with respective departure time values relative to other packets. Accordingly, the relevant output time stamp value or values for such packets without their own time stamp may be decoded from the information contained in the relevant packet by means of decoding circuitry provided therefore in the output buffer means.
The means provided for sampling the current time stamp value may be adapted so as to be controlled by a synchronisation signal provided by a Radio-Frequency (RF) demodulator circuit connected to a physical data interface carrying the data packets or frames. Subsequent to receiving and recognising e.g. a MPEG frame, the RF demodulator may generate a synchronisation signal explicitly marking the arrival time of the received MPEG frame. This synchronisation signal may subsequently be directly or indirectly used to control the sampling of the time base means of the input buffer means, thereby providing a highly accurate time-stamp value indicating the arrival time of the frame.
When a MPEG stream have been received via the input buffer means and stored in the allocated memory area of the interface unit, the processor means may be adapted to read and decode the stored MPEG frames and subsequently select MAC frames that contain a DVB MAC protocol specific 3 ms time indicator. This allows the processor means of any particular cable modem to calculate the correct output time stamp value for any particular outgoing data frame by utilising the 3 ms time indicator(s) of the selected MAC frame(s) and the arrival time stamp value or values of the selected MAC frame(s) together with previously transmitted information related to the modem""s allocated upstream slot number and its time base ranging value.
Some or all of the incoming data packets may be provided with respective time stamp values, preferably, each incoming data packet is provided with a corresponding time stamp value, since this methodology simplifies the digital hardware design and secures that all MAC frames that allows a user to transmit upstream data frames can be properly recognised and processed to maximise the users upstream message throughput.
According to a preferred embodiment of the invention, these arrival time stamp values are associated with each of the incoming data packets by inserting the time stamps into the respective data packets. For downstream transmittal of MPEG data packets or frames, a frame comprises 188 bytes and time stamps may be added as 32 bit or 4 byte values to the start of each frame so that a time stamped frame will contain a total of 192 bytes.
The clock generator means of an apparatus according to the present invention may comprise a single or several clock generators generating a first and a second clock signal. According to a preferred embodiment of the invention, the first clock signal and the second clock signal are substantially identical, i.e. of substantially same magnitude and phase. In this embodiment, the substantially identical clock signals could be the system clock signal of the apparatus and accordingly utilised to clock the processor means and the time base means. An advantage of this methodology is that clock domain related problems are avoided, thus simplifying design and verification procedures of interfaces between circuits blocks operating in different clock domains. Alternatively, the clock generator means may be adapted to generate the first clock signal and the second clock signal synchronously with respect to each other, i.e. with differing frequency and/or phase.
A single clock generator may generate a single clock signal constituting both the first and the second clock signal or a number of different clock signals with a higher and/or lower fundamental frequency than the corresponding fundamental frequency of the single clock generator through commonly known frequency multiplication and/or division techniques. Alternatively, several differing clock frequency signals may be generated by providing a corresponding number of different clock generators.
Preferably, the clock generator means generates a clock frequency signal of at least 1 MHz such as about 10 MHz or even more preferred over at least 33 MHz such as at least 66 MHz or 100 MHz. Generally, by providing higher clock frequency signals to the time base means, a better time resolution of the arrival time and departure time for incoming and outgoing data packets, respectively, is made possible.
The time base means of an apparatus according to the present invention may comprise at least one counter operating synchronously to the second clock signal. The synchronous operation with respect to the second clock signal can be accomplished by directly clocking the at least one counter with the second clock signal or with a delayed, scaled or divided/multiplied clock signal based on the second clock signal. The at least one counter is preferably of the binary counter type so that the value of a this counter provides a measure of the current time value modulo 2N, wherein N is an integer number. Preferably, a binary counter having a N value between 8 and 64 such as about 32 is utilised. A 32 bit counter, counting modulo 2{circumflex over ( )}32, will wrap around at about 65 seconds time intervals, if the counter is clocked at 66 MHz. The size of N may accordingly be scaled to the requirements of any particular application by taking into consideration the maximum unambiguous time interval that the counter must be able to resolve and the clock frequency at which it is operated.
By appropriately sampling the value of the at least one counter, as explained above in connection with using the synchronisation signal provided from e.g. the RF demodulator, a current time stamp value can be obtained and associated with e.g. the arrival time of a data packet.
According to a preferred embodiment of the invention, the time base means comprises a counter operating synchronously to the second clock signal to provide a current time stamp value of incoming data packets, and
the comparison means are adapted to utilise the current time stamp value of the counter to control departure times of outgoing data packets. By using the same counter to generate an arrival time stamp value of an incoming data packet as to control the departure time of an outgoing data packet, the interface unit hardware (often equivalent to gate count) is minimised and the timing precision is substantially equal to the precision of the clock generator means on which the second clock signal is based. Since a typical clock generator of the apparatus comprises a high precision quartz crystal based clock source, the timing of the departure time of an outgoing data packet relative to the arrival time stamp value of incoming data packets is highly accurate and easily complies with the sub-microsecond precision requirement of the DVB MAC protocol. Furthermore, the comparison means are preferably adapted to transmit an outgoing data packet when there is simple equality between the current time stamp value and the output time stamp value of an outgoing data packet to minimise the amount of circuitry required to implement this comparison function.
The interface unit memory area may be adapted to intermediately store one or several incoming data packets with associated time stamps at a time. Preferably, at least two incoming data packets, such as more than 10 data packets, or even more preferably at least 50 incoming data packets, with associated time stamps are stored at a time. By storing a large number of incoming data packets at a time, the processor overhead related to initialising and completing an interrupt routine performing reading and decoding of the large number of data packets, is made smaller. Consequently, computing resources of the processor are relieved to perform other essential data packet management operations. The downside of this methodology is that if too many incoming data packets are stored before the interrupt routine is initialised and running, at the time where the processor starts decoding these packets and recognises e.g. a MAC frame that allows upstream data packet transfer of user requests, the designated departure time of a such upstream data packet may already have expired.
According to a preferred embodiment of an apparatus according to the invention, the management of the incoming/outgoing data packets such as reading, checking, intermediately storing, decoding, output time stamping etc. those packets is performed by software running on the processor means. This software is accordingly responsible for correctly managing the incoming and outgoing data packets so as to make the apparatus comply with the relevant communication protocol or protocols of the Time Division Multiplexed System in which it operates. Preferably, this data packet management software is designated xe2x80x9cfirmwarexe2x80x9d and stored in an EEPROM or a flash memory device housed in the apparatus or, alternatively, integrated on the ASIC that also contains the processor. The apparatus may additionally comprise means for receiving remote instructions modifying the software running on the processor means so as to modify the management of the incoming and/or outgoing data packets. Accordingly, a cable modem may be provided with software updates and/or bug fixes from e.g. a central computer located at a modem manufacturers residence. In this way, a simple, fast and very cost effective method of providing cable modem users with new modem features may be provided.
This software controlled approach to data packet management is made possible by the implemented data packet time-stamping procedure within the interface unit. The time stamping relieves the processor from having to instantly accommodate the real time requirements of downstream data packet reception and decoding imposed by the high data rate of the received/transmitted data packets. The software controlled approach to data packet management in e.g. cable modems is a major advantage in comparison with prior art cable modems or set-top boxes, which traditionally have been based on specialised hard-wired processors and various-dedicated circuitry as previously explained. Alternatively, according to another embodiment of the invention, the software controlled approach to data packet management may be implemented by providing a part or all of the firmware functionality in a metal mask programmable program ROM forming part of the ASIC that also comprises the processor. This solution will still provide a faster turn-around time for updating and/or bug fixing the firmware functionality of the data packet management in the cable modems or set-top boxes than the turn-around time of traditional hard-wired processors. The metal mask programmable ROM based solution for controlling the processor may in some applications provide a more cost effective modem solution in terms of manufacturing costs than the approach based on flash memory/EEPROM.
A second aspect of the invention relates to a method for two-way data communication in a time division multiplexed system, the method comprising the steps of:
generating first and second clock signals,
providing the first clock signal to processor means,
generating a current time stamp value based on the second clock signal,
providing input buffer means receiving data of incoming data packets from a head-end system,
sampling the current time stamp value and associating the sampled value with at least some of the received incoming data packets, the time stamp value indicating an arrival time of the respective data packet,
transferring the data of the incoming data packets including data of data packets with associated time stamps to a memory of an interface unit,
generating output time stamps, each stamp having a value related to input time stamp values of selected incoming data packets,
generating outgoing data packets and associating the output time stamps with each outgoing data packet, the output time stamp value indicating a departure time of the outgoing data packet,
transferring data of the outgoing data packets with associated time stamps from the interface unit to output buffer means,
comparing the time stamp value associated with each outgoing data packet with the current time stamp value,
transmitting data of an outgoing data packet from the output buffer means to the head-end system when said time stamp values match a predetermined relationship,
thereby permitting correct time-slot alignment of outgoing data packets in the time division multiplexed system.
The method may comprise intermediately storing complete incoming data packets including complete data packets with time stamps in the input buffer means or the method may comprise just storing 8-64 bytes (equalling 2-16 d-words of 32 bits) long xe2x80x9cdata chunksxe2x80x9d of each of the incoming data packets in the input buffer means at a time. These complete data packets or xe2x80x9cdata chunksxe2x80x9d may be directly transferred to a dedicated memory area of the interface unit by means of a Direct Memory Access transfer controlled by the input buffer means. Alternatively, the method may comprise transferring the complete data packets or xe2x80x9cdata chunksxe2x80x9d to the dedicated memory area of the interface unit under control of the processor means.
The method may further comprise the step of connecting a Radio-Frequency demodulator circuit to a physical data interface carrying the data packets,
providing a synchronisation signal generated by the Radio-Frequency demodulator circuit, and
sampling the current time stamp value based on the synchronisation signal. This synchronisation signal may be generated inside the RF demodulator circuit in response to detecting the arrival of a particular type of data packet or frame. According to a preferred embodiment of the present method, the method comprises the step of inserting the time stamp value associated with an incoming data packet into the data packet. Accordingly, the time stamped data packet which stored in the interface unit memory may be a number of bytes longer, such as 4 bytes longer if 32 bit time stamps are utilised, than the received data packet. For MPEG frames of a length of 188 bytes, a such 4 bytes memory overhead per time stamped frame can be considered negligible. Preferably, the method further comprises the step of additionally inserting an output time stamp into each of the outgoing data packets.
The time base means preferably generates the current time stamp value by operating at least one counter synchronously to the second clock signal. Preferably, the second clock signal is a clock signal substantially identical to the first clock signal both having a frequency within the range between 10 and 100 MHz. According to a preferred embodiment of the present method, the current time stamp value is generated by operating a counter synchronously to the second clock signal and by sampling the value of this counter to generate the arrival time stamps for incoming data packets and to further compare this counter value with the time stamp value of each outgoing data packet and transmit the outgoing data packet when said values match.
A third aspect of the invention relates to a computer program for managing incoming data packets and generating outgoing data packets in an apparatus which provides two-way data communication in a Time Division Multiplexed System, the computer program performing the steps of:
reading time stamped data packets from a memory of an interface unit, the time stamps indicating arrival times of the respective data packets,
decoding the received data packets,
determining whether a packet comprises a time indicator that indicates allowance of upstream transmittal of an outgoing data packet and a predetermined departure time,
selecting at least some data packets comprising the time indicator,
generating the outgoing data packet,
calculating the output time stamp value associated with the outgoing data packet based on the time indicator and the arrival time stamp value of at least one selected data packet and additional transmit time information stored in the apparatus,
intermediately storing the time stamped outgoing data packet in the memory of the interface unit,
so as to allow output buffer means to read and transfer data of the outgoing time stamped data packet to output buffer means that controls the departure time of the data packet based on its associated time stamp value.
The computer program for data packet management is preferably adapted to be running on an industry standard microprocessor such as a PowerPC(copyright) processor. Most of or the entire program code is preferably stored in a Flash Memory and/or EEPROM device(s) provided within the apparatus so as to allow fast and even remote software updates and bug fixes.
The computer program may further be adapted to perform the step of: reading data based on user generated requests and generating outgoing data packets in response to the user data. This situation is typically relevant for users surfing the Internet, but as well for many other types of two-way data communication. For two-way data communication according to the DVB standard ETS 300 800, the computer program may be adapted to select incoming Media Access Control packets that contains the 3 ms time indicator of a MPEG data stream, and to generate the value of the output time stamps associated with the outgoing data packets based on the input time stamp value or values of those MAC packet or packets which contained the time indicator. The present computer program could be recorded, stored and distributed on any suitable data carrier such as hard-discs, floppy-discs, CD-ROMs, DAT-tapes, EEPROM devices, EPROM devices, PROM devices etc.